10. CACHE Instructions
10.20 Index Store Data (I)
Index Store Data (I) stores a single instruction into the primary instruction cache. The address where this instruction will be written comes from VA[13:2] of the CACHE instruction. The way where the data will be written comes from VA[0] of the CACHE instruction. The instruction itself comes from CP0 TagHi[3:0] and TagLo[31:0]. The parity bit is also stored. This comes from CP0 ECC[0]. The data to be stored bypasses the predecode and is written directly into the instruction cache. The tag field is unmodified.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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